3.3V Zero Delay Clock Buffer

The IDT2305B is a high-speed phase-lock loop (PLL) Clock Buffer designed to address high-speed Clock Distribution applications. The zero delay is achieved by aligning the phase between the incoming Clock and the output Clock operable within the range of 10 to 133MHz. The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts one reference input, and drives out five low skew Clocks The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input Clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input Clock the IDT2305B enters power down. In this mode, the device will draw less than 25A, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. The IDT2305B is characterized for both Industrial and Commercial operation. By Integrated Device Technology
IDT2305B 's PackagesIDT2305B 's pdf datasheet
IDT2305B-1DC SOIC
IDT2305B-1DC8 SOIC
IDT2305B-1DCI SOIC
IDT2305B-1DCI8 SOIC
IDT2305B-1HDC SOIC
IDT2305B-1HDC8 SOIC
IDT2305B-1HDCG SOIC
IDT2305B-1HDCG8 SOIC
IDT2305B-1HDCGI SOIC
IDT2305B-1HDCGI8 SOIC
IDT2305B-1HDCI SOIC
IDT2305B-1HDCI8 SOIC




IDT2305B Pinout, Pinouts
IDT2305B pinout,Pin out
This is one package pinout of IDT2305B,If you need more pinouts please download IDT2305B's pdf datasheet.

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