3.3V Zero Delay Clock Buffer

The IDT2309B is a high-speed phase-lock loop (PLL) Clock Buffer designed to address high-speed Clock Distribution applications. The zero delay is achieved by aligning the phase between the incoming Clock and the output Clock operable within the range of 10 to 133MHz. The IDT2309B is a 16-pin version of the IDT2305B. The IDT2309B accepts one reference input, and drives two banks of four low skew Clocks The -1H version of this device operates at up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input Clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input Clock the IDT2309B enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25A. By Integrated Device Technology
IDT2309B 's PackagesIDT2309B 's pdf datasheet
IDT2309B-1DC SOIC
IDT2309B-1DC8 SOIC
IDT2309B-1DCG SOIC
IDT2309B-1DCG8 SOIC
IDT2309B-1DCI SOIC
IDT2309B-1DCI8 SOIC
IDT2309B-1HDC SOIC
IDT2309B-1HDC8 SOIC
IDT2309B-1HDCG SOIC
IDT2309B-1HDCG8 SOIC
IDT2309B-1HDCGI SOIC
IDT2309B-1HDCGI8 SOIC
IDT2309B-1HDCI SOIC
IDT2309B-1HDCI8 SOIC
IDT2309B-1HPG TSSOP
IDT2309B-1HPG8 TSSOP
IDT2309B-1HPGG TSSOP
IDT2309B-1HPGG8 TSSOP
IDT2309B-1HPGGI TSSOP
IDT2309B-1HPGGI8 TSSOP
IDT2309B-1HPGI TSSOP
IDT2309B-1HPGI8 TSSOP




IDT2309B Pinout, Pinouts
IDT2309B pinout,Pin out
This is one package pinout of IDT2309B,If you need more pinouts please download IDT2309B's pdf datasheet.

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