3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible

The IDT23S05 is a high-speed phase-lock loop (PLL) Clock Buffer designed to address high-speed Clock Distribution applications. The zero delay is achieved by aligning the phase between the incoming Clock and the output Clock operable within the range of 10 to 133MHz. The IDT23S05 is an 8-pin version of the IDT23S09. IDT23S05 accepts one reference input, and drives out five low skew Clocks The -1H version of this device operates up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input Clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input Clock the IDT23S05 enters power down. In this mode, the device will draw less than 12A for Commercial Tempera ture range and less than 25A for Industrial temperature rang, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. By Integrated Device Technology
IDT23S05 's PackagesIDT23S05 's pdf datasheet
IDT23S05-1DC SOIC
IDT23S05-1DC8 SOIC
IDT23S05-1DCG SOIC
IDT23S05-1DCG8 SOIC
IDT23S05-1DCGI SOIC
IDT23S05-1DCGI8 SOIC
IDT23S05-1DCI SOIC
IDT23S05-1DCI8 SOIC
IDT23S05-1HDC SOIC
IDT23S05-1HDC8 SOIC
IDT23S05-1HDCG SOIC
IDT23S05-1HDCG8 SOIC
IDT23S05-1HDCGI SOIC
IDT23S05-1HDCGI8 SOIC
IDT23S05-1HDCI SOIC
IDT23S05-1HDCI8 SOIC




IDT23S05 Pinout, Pinouts
IDT23S05 pinout,Pin out
This is one package pinout of IDT23S05,If you need more pinouts please download IDT23S05's pdf datasheet.

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