3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible

The IDT23S09E is a high-speed phase-lock loop (PLL) Clock Buffer designed to address high-speed Clock Distribution applications. The zero delay is achieved by aligning the phase between the incoming Clock and the output Clock operable within the range of 10 to 200MHz. The IDT23S09E is a 16-pin version of the IDT23S05E. The IDT23S09E accepts one reference input, and drives two banks of four low skew Clocks The -1H version of this device operates up to 200MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input Clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input Clock the IDT23S09E enters power down. In this mode, the device will draw less than 12A for Commercial Temperature range and less than 25A for Industrial temperature range, and the outputs are tri-stated. By Integrated Device Technology
IDT23S09E 's PackagesIDT23S09E 's pdf datasheet
IDT23S09E-1DC SOIC
IDT23S09E-1DC8 SOIC
IDT23S09E-1DCG SOIC
IDT23S09E-1DCG8 SOIC
IDT23S09E-1DCI SOIC
IDT23S09E-1DCI8 SOIC
IDT23S09E-1HDC SOIC
IDT23S09E-1HDC8 SOIC
IDT23S09E-1HDCGI SOIC
IDT23S09E-1HDCGI8 SOIC
IDT23S09E-1HDCI SOIC
IDT23S09E-1HDCI8 SOIC
IDT23S09E-1HPG TSSOP
IDT23S09E-1HPG8 TSSOP
IDT23S09E-1HPGG TSSOP
IDT23S09E-1HPGG8 TSSOP
IDT23S09E-1HPGGI TSSOP
IDT23S09E-1HPGGI8 TSSOP
IDT23S09E-1HPGI TSSOP
IDT23S09E-1HPGI8 TSSOP




IDT23S09E Pinout, Pinouts
IDT23S09E pinout,Pin out
This is one package pinout of IDT23S09E,If you need more pinouts please download IDT23S09E's pdf datasheet.

IDT23S09E Application circuits
IDT23S09E circuits
This is one application circuit of IDT23S09E,If you need more circuits,please download IDT23S09E's pdf datasheet.


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IDT23S09E Application Notes IDT23S09E RoHS IDT23S09E Circuits IDT23S09E footprint