2.5V Zero Delay Clock Buffer, Spread Spectrum Compatible

The IDT23S09T is a high-speed phase-lock loop (PLL) Clock Buffer designed to address high-speed Clock Distribution applications. The zero delay is achieved by aligning the phase between the incoming Clock and the output Clock operable within the range of 10 to 133MHz. The IDT23S09T is a 16-pin version of the IDT23S05T. The IDT23S09T accepts one reference input, and drives two banks of four low skew Clocks All parts have on-chip PLLs which lock to an input Clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input Clock the IDT23S09T enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 12A By Integrated Device Technology
IDT23S09T 's PackagesIDT23S09T 's pdf datasheet
IDT23S09T-1DC SOIC
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IDT23S09T-1DCG8 SOIC




IDT23S09T Pinout, Pinouts
IDT23S09T pinout,Pin out
This is one package pinout of IDT23S09T,If you need more pinouts please download IDT23S09T's pdf datasheet.

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