2.5V Differential 1:5 Clock Buffer TeraBufferThe IDT5T915 2.5V differential (DDR) Clock Buffer is a user-selectable
single-ended or differential input to five differential outputs built on advanced
metal CMOS technology. The differential Clock Buffer fanout from a single or
differential input to five differential or single-ended outputs reduces loading on
the preceding driver and provides an efficient Clock Distribution network. The
IDT5T915 CAN act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable Interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels. By Integrated Device Technology
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IDT5T915 Pb-Free | IDT5T915 Cross Reference | IDT5T915 Schematic | IDT5T915 Distributor |
IDT5T915 Application Notes | IDT5T915 RoHS | IDT5T915 Circuits | IDT5T915 footprint |