2.5V LVDS 1:2 Glitchless Clock Buffer Terabuffer II

The IDT5T93GL02 2.5V differential Clock Buffer is a user-selectable differ- ential input to two LVDs outputs . The fanout from a differential input to two LVDs outputs reduces loading on the preceding driver and provides an efficient Clock distribution network. The IDT5T93GL02 CAN act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDs input to LVDs outputs. A single-ended 3.3V / 2.5V LVTTL input CAN also be used to translate to LVDs outputs. The redundant input capability allows for a glitchless change-over from a primary Clock source to a secondary Clock source up to 450MHz. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three Clock cycles of the previously-selected input Clock The outputs will remain low for up to three Clock cycles of the newly- selected Clock after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a Clock source is absent or is driven to DC levels below the minimum specifications. By Integrated Device Technology
IDT5T93GL02 's PackagesIDT5T93GL02 's pdf datasheet
IDT5T93GL02PGGI TSSOP
IDT5T93GL02PGGI8 TSSOP
IDT5T93GL02PGI TSSOP
IDT5T93GL02PGI8 TSSOP




IDT5T93GL02 Pinout, Pinouts
IDT5T93GL02 pinout,Pin out
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