128k X 36, 256k X 18 3.3v Synchronous Srams 2.5v I/o, Flow-through Outputs Burst Counter, Single Cycle Deselect -

The IDT71V2577 IDT71V2579 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V2577 IDT71V2579 SRAMs contain write, data, address and control Registers There are no Registers in the data output path (flow-through architecture). Internal Logic allows the SRAM to generate a self-timed write based upon a decision which CAN be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V2577 IDT71V2579 CAN provide four cycles of data for a single address presented to the SRAM An internal burst address Counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising Clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising Clock edges. The order of these three addresses are defined by the internal burst Counter and the LBO input pin. The IDT71V2577 IDT71V2579 SRAMs utilize IDTs latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). By Integrated Device Technology
IDT71V2579 's PackagesIDT71V2579 's pdf datasheet

IDT71V2579 Pinout, Pinouts
IDT71V2579 pinout,Pin out
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