256k X 18 3.3v Synchronous Zbt Sram 3.3v I/o, Burst Counter Pipelined Outputs

The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMs They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one Clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V3548 contain data I/O, address and control signal Registers Output enable is the only asynchronous signal and CAN be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V3548 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device Registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation CAN be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V3548 has an on-chip burst Counter In the burst mode, the IDT71V3548 CAN provide four cycles of data for a single address presented to the SRAM The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst Counter (ADV/LD = HIGH). By Integrated Device Technology
IDT71V3548SA 's PackagesIDT71V3548SA 's pdf datasheet

IDT71V3548SA Pinout, Pinouts
IDT71V3548SA pinout,Pin out
This is one package pinout of IDT71V3548SA,If you need more pinouts please download IDT71V3548SA's pdf datasheet.

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