32Q X36 2Mb Multi-Queue, 1.8V

The IDT72P51539 IDT72P51549 IDT72P51559 IDT72P51569 multi-queue flow-con- trol devices are single chips with up to 32 Discrete configurable FIFO queues. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a specific queue via an internal de-multiplex operation, addressed by the write address bus (WRADD). Data read from the read port is accessed from a specific queue via an internal multiplex operation, addressed by the read address bus (RDADD). Data writes and reads CAN be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. By Integrated Device Technology
IDT72P51559 's PackagesIDT72P51559 's pdf datasheet
IDT72P51559L5BB PBGA
IDT72P51559L5BB8 PBGA
IDT72P51559L6BB PBGA
IDT72P51559L6BB8 PBGA
IDT72P51559L6BBI PBGA
IDT72P51559L6BBI8 PBGA




IDT72P51559 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
IDT72P51559 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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