8Q X36 512K Multi-Queue, 3.3V

The IDT72V51336 IDT72V51346 IDT72V51356 multi-queue flow-control de- vices are single chip within which anywhere between 1 and 8 Discrete FIFO queues CAN be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads CAN be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. By Integrated Device Technology
IDT72V51336 's PackagesIDT72V51336 's pdf datasheet
IDT72V51336L6BB PBGA
IDT72V51336L6BB8 PBGA
IDT72V51336L7-5BB PBGA
IDT72V51336L7-5BB8 PBGA
IDT72V51336L7-5BBI PBGA




IDT72V51336 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
IDT72V51336 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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