16-Bit Registered/Latched Transceiver

The IDT74FCT162511T 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines D-type Latches and D-type Flip-Flops to allow data flow in transparent, latched, or clocked modes. The device has a parity generator/ checker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags are open drain outputs which CAN be tied together and/or tied with flags from other devices to form a single error flag or interrupt. The parity error flags are enabled by the OExx control pins allowing the designer to disable the error flag during combinational transitions. By Integrated Device Technology
IDT74FCT162511T 's PackagesIDT74FCT162511T 's pdf datasheet
IDT74FCT162511ATPA TSSOP
IDT74FCT162511ATPA8 TSSOP
IDT74FCT162511ATPAG TSSOP
IDT74FCT162511ATPAG8 TSSOP
IDT74FCT162511ATPV SSOP
IDT74FCT162511ATPV8 SSOP
IDT74FCT162511ATPVG SSOP
IDT74FCT162511ATPVG8 SSOP
IDT74FCT162511CTPA TSSOP
IDT74FCT162511CTPA8 TSSOP
IDT74FCT162511CTPAG TSSOP
IDT74FCT162511CTPAG8 TSSOP
IDT74FCT162511CTPV SSOP
IDT74FCT162511CTPV8 SSOP
IDT74FCT162511CTPVG SSOP
IDT74FCT162511CTPVG8 SSOP




IDT74FCT162511T Pinout, Pinouts
IDT74FCT162511T pinout,Pin out
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