14-bit 1:2 Registered Buffer With Parity - Integrated Device Technology

The SSTU32D869 is a 14-bit 1:2 configurable registered Buffer designed for 1.7V to 1.9V VDD operation. All Clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32D869 operates from a differential Clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The SSTU32D869 includes a parity checking function. The SSTU32D869 accepts parity bits from the Memory controller at its input pins PARIN[1:2], compares it with the data received on the D-inputs, and indicates whether a parity error has occured on its open-drain PTYERR[1:2] pins (active low). When used as a single device, the C1 inputs are tied low. In this configuration, the partial-parity-out (PPO[1:2]) and PTYERR[1:2] signals are produced two Clock cycles after the corresponding data output. When used in pairs, the C1 inputs of the first Register are tied low and the C1 inputs of the second Register are tied high. The PTYERR[1:2] outputs of the first SSTU32D869 is left floating and the valid error information is latched on the PTYERR[1:2] outputs of the second SSTU32D869 . By Integrated Device Technology
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IDT74SSTU32D869 Pinout, Pinouts
IDT74SSTU32D869 pinout,Pin out
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