2.5V - 2.6V PLL Differential 1:10 SDRAM Clock Driver

The CSPT857C is a PLL based Clock Driver that acts as a zero delay Buffer to distribute one differential Clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback Clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. A CMOS Enable/Disable pin is available for low power disable. When the input frequency falls below approximately 20MHz, the device will enter power down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output Clock Drivers are tristated, resulting in a current consumption of less than 200. By Integrated Device Technology
IDTCSPT857C 's PackagesIDTCSPT857C 's pdf datasheet
IDTCSPT857CBVG BGA
IDTCSPT857CBVG8 BGA
IDTCSPT857CNLG VFQFPN
IDTCSPT857CNLG8 VFQFPN
IDTCSPT857CNLGI VFQFPN
IDTCSPT857CNLGI8 VFQFPN
IDTCSPT857CPAG TSSOP
IDTCSPT857CPAG8 TSSOP




IDTCSPT857C Pinout, Pinouts
IDTCSPT857C pinout,Pin out
This is one package pinout of IDTCSPT857C,If you need more pinouts please download IDTCSPT857C's pdf datasheet.

IDTCSPT857C circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

IDTCSPT857C Pb-Free IDTCSPT857C Cross Reference IDTCSPT857C Schematic IDTCSPT857C Distributor
IDTCSPT857C Application Notes IDTCSPT857C RoHS IDTCSPT857C Circuits IDTCSPT857C footprint