1.8V PLL Differential 1:10 SDRAM Clock Driver

The IDTCSPU877 is a PLL based Clock Driver that acts as a zero delay Buffer to distribute one differential Clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback Clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode Logic When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential Clock inputs (CLK, CLK) are both at Logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output Clock Drivers are disabled, resulting in a current consumption device of less than 500. By Integrated Device Technology
IDTCSPU877 's PackagesIDTCSPU877 's pdf datasheet

IDTCSPU877 Pinout, Pinouts
IDTCSPU877 pinout,Pin out
This is one package pinout of IDTCSPU877,If you need more pinouts please download IDTCSPU877's pdf datasheet.

IDTCSPU877 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

IDTCSPU877 Pb-Free IDTCSPU877 Cross Reference IDTCSPU877 Schematic IDTCSPU877 Distributor
IDTCSPU877 Application Notes IDTCSPU877 RoHS IDTCSPU877 Circuits IDTCSPU877 footprint