4Meg X 32 128-MBIT SYNCHRONOUS DRAM

's 128Mb Synchronous DRAM achieves high-speed ISSI data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the Clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. Note: This is a summary datasheet specific to the die format. Please refer to the IS42S32400D for complete device specification. By Integrated Silicon Solution, Inc.
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