In-System Programmable Clock Generator With Universal Fan-Out Buffer

The ISPCLOCK5510 and ispClock5520 are in-system-programmable high-fanout PLL-based Clock Drivers designed for use in high performance Communications and computing applications. The ISPCLOCK5510 provides up to 10 sin- gle-ended or ve differential Clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential Clock outputs. Each pair of outputs may be independently congured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro- grammable control of termination, slew-rate, and Timing skew. All conguration information is stored on-chip in non- volatile E2 CMOS memory. The ispClock5500s PLL and divider systems supports the synthesis of Clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of ve post-PLL V-divid- ers provides additional exibility by supporting the generation of ve separate output frequencies. Loop feedback may be taken from the output of any of the ve V-dividers. The core functions of all members of the ispClock5500 family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional block diagrams of the ISPCLOCK5510 and ispClock5520. By Lattice Semiconductor Corp.
ISPCLOCK5510 's PackagesISPCLOCK5510 's pdf datasheet
ISPPAC-CLK5510V-01T48C TQFP
ISPPAC-CLK5520V-01T100C TQFP
ISPPAC-CLK5510V-01T48I TQFP
ISPPAC-CLK5520V-01T100I TQFP
ISPPAC-CLK5510V-01TN48C TQFP
ISPPAC-CLK5520V-01TN100C TQFP
ISPPAC-CLK5510V-01TN48I TQFP
ISPPAC-CLK5520V-01TN100I TQFP




ISPCLOCK5510 Pinout, Pinouts
ISPCLOCK5510 pinout,Pin out
This is one package pinout of ISPCLOCK5510,If you need more pinouts please download ISPCLOCK5510's pdf datasheet.

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