In-System Programmable High Density PLD

The ISPLSI3320 is a High-Density Programmable Logic Device containing 480 Registers 160 Universal I/O pins, five Dedicated Clock Input Pins, ten Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ISPLSI3320 features 5V in-system pro- grammability and in-system diagnostic capabilities. The ISPLSI3320 offers non-volatile reprogrammability of the Logic as well as the interconnect to provide truly reconfigurable systems. The basic unit of Logic on the ISPLSI3320 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...J3. There are a total of 40 of these Twin GLBs in the ISPLSI3320 device. Each Twin GLB has 24 inputs, a program- mable AND array and two OR/Exclusive-OR Arrays, and eight outputs which CAN be configured to be either com- binatorial or registered. All Twin GLB inputs come from the GRP. By Lattice Semiconductor Corp.
ISPLSI3320 's PackagesISPLSI3320 's pdf datasheet
ISPLSI3320-100LB320 PQFP
ISPLSI3320-70LB320 BGA

ISPLSI3320 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
ISPLSI3320 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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ISPLSI3320 Application Notes ISPLSI3320 RoHS ISPLSI3320 Circuits ISPLSI3320 footprint
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