1Gb D-die DDR3 SDRAM Specification

The 1Gb DDR3 SDRAM ( K4B1G0446D K4B1G0846D K4B1G1646D )D-die is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This syn- chronous device achieves high speed double-data-rate transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM fea- tures such as posted CAS, Programmable CWL, Internal (Self) Calibra- tion, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of exter- nally supplied differential Clocks Inputs are latched at the crosspoint of dif- ferential Clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash- ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V 0.075V powersupply and 1.5V 0.075V VDDQ. The 1Gb DDR3 D-die device is available in 82ball FBGAs(x4/x8) and 100ball FBGA(x16) By Samsung Semiconductor, Inc.
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