DDP 2Gb E-die DDR3 SDRAM Specification

The DDP 2Gb DDR3 SDRAM E-die is organized as a 64Mbit x 4 I/Os x 8banks, 32Mbit x 8 I/Os x 8banks. This synchronous device achieves high speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR3- 1333) for general applications. The chip is designed to comply with the following key DDR3 SDRAM fea- tures such as posted CAS, Programmable CWL, Internal (Self) Calibra- tion, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of exter- nally supplied differential Clocks Inputs are latched at the crosspoint of dif- ferential Clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash- ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ. The 2Gb DDR3 E-die device is available in 78ball FBGAs(x4/x8). By Samsung Semiconductor, Inc.
K4B2G0446E 's PackagesK4B2G0446E 's pdf datasheet
K4B2G0846E
K4B2G0446E-MCF7
K4B2G0446E-MCF8
K4B2G0446E-MCH9
K4B2G0846E-MCF7
K4B2G0846E-MCF8
K4B2G0846E-MCH9

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K4B2G0446E Pinout, Pinouts
K4B2G0446E pinout,Pin out
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