256Mb J-die DDR SDRAM Specification

, Double-data-rate architecture; two data transfers per Clock cycle , Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) , Four banks operation , Differential Clock inputs(CK and CK) , DLL aligns DQ and DQS transition with CK transition , MRS cycle with address key programs -. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) , All inputs except data & DM are sampled at the positive going edge of the system clock(CK) , Data I/O transactions on both edges of data strobe , Edge aligned data output, center aligned data input , LDM,UDM for write masking only (x16) , DM for write masking only (x4, x8) , Auto & Self refresh , 7.8us refresh interval(8K/64ms refresh) , Maximum burst refresh cycle : 8 , 66pin TSOP II Pb-Free & Halogen-Free package By Samsung Semiconductor, Inc.
K4H560838J 's PackagesK4H560838J 's pdf datasheet
K4H560838J-LCB3 TSOP
K4H560838J-LCCC TSOP




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K4H560838J Application circuits
K4H560838J circuits
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