64Mb N-die DDR SDRAM Specification

64Mb N-die DDR SDRAM K4H641638N Specification ,, VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333, 4 , Double-data-rate architecture; two data transfers per Clock cycle , Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) , Four banks operation , Differential Clock inputs(CK and CK) , DLL aligns DQ and DQS transition with CK transition , MRS cycle with address key programs -. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) , All inputs except data & DM are sampled at the positive going edge of the system clock(CK) , Data I/O transactions on both edges of data strobe , Edge aligned data output, center aligned data input , LDM,UDM for write masking only (x16) , DM for write masking only (x4, x8) , Auto & Self refresh , 15.6us refresh interval(4K/64ms refresh) , Maximum burst refresh cycle : 8 , 66pin TSOP II Pb-Free and Halogen-Free package , 60ball FBGA Pb-Free and Halogen-Free package By Samsung Semiconductor, Inc.
K4H641638N 's PackagesK4H641638N 's pdf datasheet
K4H641638N-FCCC TSOP
K4H641638N-LCB3 TSOP
K4H641638N-LCCC TSOP




K4H641638N Pinout, Pinouts
K4H641638N pinout,Pin out
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