512Mbit GDDR2 SDRAM

The 512Mb gDDR2 SDRAM chip is organized as 8Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed graphic double-data-rate transfer rates of up to 500MHz for general applications. The chip is designed to comply with the following key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential Clocks Inputs are latched at the cross point of differential Clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidi- rectional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 512Mb(x16) device receive 13/10/2 addressing. The 512Mb gDDR2 devices are available in 84ball FBGAs(x16). By Samsung Semiconductor, Inc.
K4N51163QZ 's PackagesK4N51163QZ 's pdf datasheet
K4N51163QZ-HC20
K4N51163QZ-HC25




K4N51163QZ Pinout, Pinouts
K4N51163QZ pinout,Pin out
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