256mbit Gddr2 Sdram Semiconductor

The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed graphic double-data-rate transfer rates of up to 1000Mb/sec/pin for general applications. The chip is designed to comply with the following key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential Clocks Inputs are latched at the cross point of differential Clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirec- tional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 256Mb(x16) device receive 13/9/2 address- ing. The 256Mb gDDR2 devices operate with a single 1.8V 0.1V power supply and 1.8V 0.1V VDDQ. The 256Mb gDDR2 devices are available in 84ball FBGAs(x16). By Samsung Semiconductor, Inc.
K4N56163QF-GC 's PackagesK4N56163QF-GC 's pdf datasheet
K4N56163QF-GC25 FBGA
K4N56163QF-GC30 FBGA
K4N56163QF-GC37 FBGA

K4N56163QF-GC Pinout, Pinouts
K4N56163QF-GC pinout,Pin out
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