32Mx16 Mobile DDR SDRAM32Mx16 Mobile DDR SDRAM , K4X51163PE , Double-data-rate architecture; two data transfers per Clock cycle
, Bidirectional data strobe(DQS)
, Four banks operation
, Differential Clock inputs(CK and CK)
, MRS cycle with address key programs
- CAS Latency ( 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
, EMRS cycle with address key programs
- Partial Array Self Refresh ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
, Internal Temperature Compensated Self Refresh
, All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
, Data I/O transactions on both edges of data strobe, DM for masking.
, Edge aligned data output, center aligned data input.
, No DLL; CK to DQS is not synchronized.
, DM0 - DM3 for write masking only. By Samsung Semiconductor, Inc.
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