16M X32 Mobile-DDR SDRAM

16M x32 Mobile-DDR SDRAM , K4X51323PC , 1.8V power supply, 1.8V I/O power , Double-data-rate architecture; two data transfers per Clock cycle , Bidirectional data strobe(DQS) , Four banks operation , 1 /CS , 1 CKE , Differential Clock inputs(CK and CK) , MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) , Internal Temperature Compensated Self Refresh , Deep Power Down Mode , All inputs except data & DM are sampled at the positive going edge of the system clock(CK). , Data I/O transactions on both edges of data strobe, DM for masking. , Edge aligned data output, center aligned data input. , No DLL; CK to DQS is not synchronized. , DM0 - DM3 for write masking only. By Samsung Semiconductor, Inc.
K4X51323PC 's PackagesK4X51323PC 's pdf datasheet
K4X51323PC-8GC30 FBGA

K4X51323PC Pinout, Pinouts
K4X51323PC pinout,Pin out
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