16Mb Sync. Pipelined SRAM Specification

The K7A163600A and K7A161800A are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(32/18) bits and integrates address and control Registers a 2-bit burst address Counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control sig- nals. By Samsung Semiconductor, Inc.
K7A161800A 's PackagesK7A161800A 's pdf datasheet

K7A161800A Pinout, Pinouts
K7A161800A pinout,Pin out
This is one package pinout of K7A161800A,If you need more pinouts please download K7A161800A's pdf datasheet.

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