36Mb Sync. Pipelined Burst SRAM Specification

The K7A323600M and K7A321800M are 37,748,736-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 1M(2M) words of 36(18) bits and inte- grates address and control Registers a 2-bit burst address Counter and added some new functions for high perfor- mance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control sig- nals. By Samsung Semiconductor, Inc.
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K7A323600M Pinout, Pinouts
K7A323600M pinout,Pin out
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