36Mb Sync. Pipelined Burst SRAM Specification

The K7A323600M and K7A321800M are 37,748,736-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 1M(2M) words of 36(18) bits and inte- grates address and control Registers a 2-bit burst address Counter and added some new functions for high perfor- mance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control sig- nals. By Samsung Semiconductor, Inc.
K7A323600M 's PackagesK7A323600M 's pdf datasheet



K7A323600M Pinout, Pinouts
K7A323600M pinout,Pin out
This is one package pinout of K7A323600M,If you need more pinouts please download K7A323600M's pdf datasheet.

K7A323600M circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

K7A323600M Pb-Free K7A323600M Cross Reference K7A323600M Schematic K7A323600M Distributor
K7A323600M Application Notes K7A323600M RoHS K7A323600M Circuits K7A323600M footprint
Hot categories