256Kx36 & 512Kx18 Synchronous SRAM

The K7A803601M and K7A801801M are 9,437,184-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36(18) bits and inte- grates address and control Registers a 2-bit burst address Counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is per- formed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle CAN be initiated with either the By Samsung Semiconductor, Inc.
K7A803601M 's PackagesK7A803601M 's pdf datasheet
K7A801801M




K7A803601M Pinout, Pinouts
K7A803601M pinout,Pin out
This is one package pinout of K7A803601M,If you need more pinouts please download K7A803601M's pdf datasheet.

K7A803601M circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

K7A803601M Pb-Free K7A803601M Cross Reference K7A803601M Schematic K7A803601M Distributor
K7A803601M Application Notes K7A803601M RoHS K7A803601M Circuits K7A803601M footprint
Hot categories