36Mb DDRII SRAM Specification

The K7J323682C and K7J321882C are 37,748,736-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs They are orga- nized as 1,048,576 words by 36bits for K7J323682C and 2,097,152 words by 18 bits for K7J321882C. The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports. Mem- ory bandwidth is higher than DDR SRAM without separate input output as separate read and write ports eliminate bus turn around cycle. By Samsung Semiconductor, Inc.
K7J321882C 's PackagesK7J321882C 's pdf datasheet

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K7J321882C Application circuits
K7J321882C circuits
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