128kx36 & 256kx18-bit Pipelined Ntramtm

The K7N403601A and K7N401801A are 4,718,592 bits Syn- chronous Static SRAMs The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input Clock Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the Clock input. This feature eliminates complex off- chip write pulse generation and provides increased Timing flexibility for incomming sig- nals. For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output Register and then released to the output bufferes at the next rising edge of Clock The K7N403601A and K7N401801A are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. By Samsung Semiconductor, Inc.
K7N401801A 's PackagesK7N401801A 's pdf datasheet

K7N401801A Pinout, Pinouts
K7N401801A pinout,Pin out
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