256k X 36 & 512k X 18 Pipelined N-t Ram - Tm Semiconductor

The K7N803645M and K7N801845M are 9,437,184 bits Syn- chronous Static SRAMs The NtRAMTM, or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input Clock Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the Clock input. This feature eliminates complex off-chip write pulse generation and provides increased Timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output Register and then released to the output Buffers at the next rising edge of Clock The K7N803645M and K7N801845M are implemented with SAMSUNGs high performance CMOS technology and is avail- able in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. By Samsung Semiconductor, Inc.
K7N801845M 's PackagesK7N801845M 's pdf datasheet
K7N803645M




K7N801845M Pinout, Pinouts
K7N801845M pinout,Pin out
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