128kx36 & 256kx18 Synchronous Pipelined Sram Semiconductor

The K7P403622M and K7P401822M are 4,718,592 bit Synchronous Pipeline Mode SRAM It is organized as 131,072words of 36 bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNG s advanced CMOS technology. Single differential PECL level K Clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K Clock All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from output Registers edge of the next rising edge of K Clock An internal write data Buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch. By Samsung Semiconductor, Inc.
K7P401822M 's PackagesK7P401822M 's pdf datasheet
K7P403622M-H20
K7P403622M-H16
K7P403622M-H19
K7P401822M-H20
K7P401822M-H16
K7P401822M-H19
K7P403622M




K7P401822M Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
K7P401822M circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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K7P401822M Application Notes K7P401822M RoHS K7P401822M Circuits K7P401822M footprint
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