256kx36 & 512kx18 Sram Semiconductor

The K7P803611M and K7P801811M are 9,437,184 bit Synchronous Pipeline Mode SRAM It is organized as 262,144 words of 36 bits(or 524,288 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology. Single differential HSTL level K Clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K Clock All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from output Registers edge of the next rising edge of the K Clock An internal write data Buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch. By Samsung Semiconductor, Inc.
K7P801811M 's PackagesK7P801811M 's pdf datasheet
K7P803611M
K7P803611M-H25
K7P803611M-H21
K7P803611M-H20
K7P801811M-H25
K7P801811M-H21
K7P801811M-H20




K7P801811M Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
K7P801811M circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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K7P801811M Application Notes K7P801811M RoHS K7P801811M Circuits K7P801811M footprint