512mb Nand*2 256mb Mobile Sdram*2 Semiconductor

The KBE00F005A is a Multi Chip Package Memory which combines 1Gbit Nand Flash Memory(organized with two pieces of 512Mbit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM) 1Gbit NAND Flash memory is organized as 128M x8 bits and 512Mbit Mobile SDRAM is organized as 4M x32 bits x4 banks In 1Gbit NAND Flash its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program oper- ation CAN be performed in typically 200s on the 528-byte page and an erase operation CAN be performed in typically 2ms on a 16K- byte block. Data in the data Register CAN be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse rep- etition, where required, and internal verify and margining of data. Even the write-intensive systems CAN take advantage of the extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable appli- cations requiring non-volatility. In 512Mbit SDRAM Synchronous design make a device controlled precisely with the use of system Clock and I/O transactions are possible on every Clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The KBE00F005A is suitable for use in data memory of mobile Communication system to reduce not only mount area but also power consumption. This device is available in 137-ball FBGA Type. By Samsung Semiconductor, Inc.
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KBE00F005A-D411 Pinout, Pinouts
KBE00F005A-D411 pinout,Pin out
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