KK16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter). Each channel CAN be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of error data per byte CAN be stored in both receive and transmit modes. Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU CAN read the complete status of the UART at any time during the functional operation. The Status information includes the type and condition of the transfer operations being performed by the UART as well as any error conditions such as parity, overrun, framing, and break interrupt. KK16C554 includes a programmable baud rate generator which is capable of dividing the Timing reference Clock input by divisors of 1 to 216 -1, and producing a 16x Clock for driving the internal transmitter Logic Provisions are also included to use this Clock to drive the receiver Logic KK16C554 has complete MODEM-control capability and an interrupt system that CAN be programmed to the user’s requirements, minimizing the computing required to handle the Communication links. By Kodenshi Korea Corp.
KK16C554 's PackagesKK16C554 's pdf datasheet

KK16C554 Pinout, Pinouts
KK16C554 pinout,Pin out
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