Quad Clocked ?d? Latch High-voltage Silicon-gate Cmos Korea Corp.

KK4042B types contain four latch circuits, each strobed by a common Clock Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and Q during the Clock level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 Clock level and for POLARITY = 1 the transfer occurs during the 1 Clock level. The outputs follow the data input providing the Clock and POLARITY levels defined above are present. When a Clock transition occurs (positive for POLARITY = 0 and negative for POLARTY = 1) the information present at the input during the Clock transition is retained at the outputs until an opposite Clock transition occurs. The KK4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes); 16-lead dual-in-line plastic package (E suffix), and in chip form (H suffix). By Kodenshi Korea Corp.
KK4042B 's PackagesKK4042B 's pdf datasheet
KK4042BN
KK4042BD




KK4042B Pinout, Pinouts
KK4042B pinout,Pin out
This is one package pinout of KK4042B,If you need more pinouts please download KK4042B's pdf datasheet.

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