128kx36 & 256kx18 Synchronous Pipelined Sram Semiconductor

The KM736FV4021 and KM718FV4021 are 4,718,592 bit Synchronous Pipeline Mode SRAM It is organized as 131,072words of 36 bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology. Single differential PECL level K Clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K Clock All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from output Registers edge of the next rising edge of the K Clock An internal write data Buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch. By Samsung Semiconductor, Inc.