4 X 8-bit Multilevel Pipeline Register - Logic Devices Incorporated

The L29C520 and L29C521 are pin- for-pin compatible with the IDT29FCT520/IDT29FCT521 and AMD Am29520/Am29521, imple- mented in low power CMOS. The L29C520 and L29C521 contain four Registers which CAN be configured as two independent, 2-level pipelines or as one 4-level pipeline. The Instruction pins, I1-0, control the loading of the Registers For either device, the Registers may be config- ured as a four-stage Delay Line with data loaded into R1 and shifted sequentially through R2, R3, and R4. Also, for the L29C520 data may be loaded from the inputs into either R1 or R3 with only R2 or R4 shifting. The L29C521 differs from the L29C520 in that R2 and R4 remain unchanged during this type of data load, as shown in Tables 1 and 2. Finally, I1-0 may be set to prevent any Register from changing. By LOGIC Devices Incorporated
L29C520 's PackagesL29C520 's pdf datasheet

L29C520 Pinout, Pinouts
L29C520 pinout,Pin out
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