Dual Pipeline Register

The L29C525 is a high-speed, low power CMOS pipeline Register It is pin-for-pin compatible with the AMD Am29525. The L29C525 CAN be configured as two independent 8-level pipelines or as a single 16-level pipeline. The configuration imple- mented is determined by the instruc- tion code (I1-0) as shown in Table 2. The I1-0 instruction code controls the internal routing of data and loading of each Register For instruction I1-0 = 00 (Push A and B), data applied at the D7-0 inputs is latched into Register A0 on the rising edge of CLK. The contents of A0 simultaneously move to Register A1, A1 moves to A2, and so on. The contents of Register A7 are wrapped back to Register B0. The Registers on the B side are similarly shifted, with the contents of Register B7 lost. By LOGIC Devices Incorporated
L29C525 's PackagesL29C525 's pdf datasheet
L29C525PC20
L29C525PC15
L29C525JC20
L29C525JC15




L29C525 Pinout, Pinouts
L29C525 pinout,Pin out
This is one package pinout of L29C525,If you need more pinouts please download L29C525's pdf datasheet.

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