12 X 12-bit Parallel Multiplier

The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchildss MPY112K. The A and B input operands are loaded into their respective Registers on the rising edge of the separate Clock inputs (CLK A and CLK B). Twos complement or unsigned magnitude operands are accommo- dated via the operand control bit (TC) which is loaded along with the B operands. The operands are specified to be in twos complement format when TC is asserted and unsigned magnitude when TC is deasserted. Mixed mode operation is not allowed. By LOGIC Devices Incorporated
LMU112 's PackagesLMU112 's pdf datasheet

LMU112 Pinout, Pinouts
LMU112 pinout,Pin out
This is one package pinout of LMU112,If you need more pinouts please download LMU112's pdf datasheet.

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