16 X 16-bit Parallel Multiplier

The LMU217 is a high-speed, low power 16-bit parallel multiplier. The LMU217 produces the 32-bit prod- uct of two 16-bit numbers. Data present at the A inputs, along with the TCA control bit, is loaded into the A Register on the rising edge of CLK. B data and the TCB control bit are similarly loaded. Loading of the A and B Registers is controlled by the ENA and ENB controls. When HIGH, these con- trols prevent application of the Clock to the respective Register The TCA and TCB controls specify the operands as twos complement when HIGH, or unsigned magnitude when LOW. By LOGIC Devices Incorporated