CD4504B hex voltage level-shifter consists of six circuits which shift input signals from the VCC logic level to the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state. When the SELECT input is a LOW ...
The HD74LV2GT240A has dual bus buffer inverted with 3state output in an 8 pin package. Tw
inverters are included in one circuit. Each circuit can be independently controlled by the enable signal 1OE
or 2OE, which enables outputs when receiving a low-level ...
The HD74LV2GT241A has dual bus buffer noninverted with 3state output in an 8 pin package. Tw
noninverters are included in one circuit. Each circuit can be independently controlled by the enable signal
OE or OE, which enables outputs when receiving a low or ...
The HD74LV2GT245A has two buffers with three state output in a 8 pin package. When DIR is high, data
is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs
to the A outputs. The A and B buses are ...
The HD74LV2GT32A has dual two-input OR gates in an 8 pin package. The input protection circuitry on
this device allows over voltage tolerance on the input, allowing the device to be used as a logicleve
translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or ...
The HD74LV2GT34A has triple noninverters in an 8 pin package. The input protection circuitry on this
device allows over voltage tolerance on the input, allowing the device to be used as a logiclevel translato
from 3.0 V CMOS Logic to 5.0 V CMOS Logic or ...
The HD74LV2GT74A has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin
package. The input data is transferred to the output at the rising edge of clock pulse CLK. The input
protection circuitry on this device allows over voltage ...
The HD74LV2GT86A performs the Boolean functions Y = A ,B or Y = AB + AB in positive logic. A
common application is as a true / complement element. If one of the inputs is low, the other input will be
reproduced in true form at the output. If one of the ...
The HD74LV1GT125A has a bus buffer gate with 3state output in a 5 pin package. Output is disabled when the
associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE
should be connected to VCC through ...
The HD74LV1GT126A has a bus buffer gate with 3state output in a 5 pin package. Output is disabled when the
associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE
should be connected to VCC through ...
The HD74LV1GT14A is high-speed CMOS schmitt-trigger inverter using silicon gate CMOS process. With CMOS
low power dissipation, it provides high-speed equivalent to LSTTL series. Te internal circuit of three stages
construction with buffer provides wide ...
The HD74LV1GT32A is high-speed CMOS two input OR gate using silicon gate CMOS process. With CMOS low
power dissipation, it provides high-speed equivalent to LSTTL series. The interna circuit of three stages construction
with buffer provides wide noise ...
The HD74LV2GT04A has triple inverters in an 8 pin package. The input protection circuitry on this device
allows over voltage tolerance on the input, allowing the device to be used as a logiclevel translator fro
3.0 V CMOS Logic to 5.0 V CMOS Logic or from ...
The HD74LV2GT08A has dual two-inputs AND gates in a 8 pin package. The input protection circuitry
on this device allows over voltage tolerance on the input, allowing the device to be used as a logicleve
translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic ...
The HD74LV2GT123A features output pulse duration control by three methods. In the first method, the A
input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B ...
The HD74LV2GT125A has dual bus buffer with 3state output in an 8 pin package. Output is disable
when the associated output enable (OE) input is high. To ensure the high impedance state during power up
or power down, OE should be connected to VCC through a ...
The HD74LV2GT126A has dual bus buffer with 3state output in a 8 pin package. Output is disable
when the associated output enable (OE) input is low. To ensure the high impedance state during power up
or power down, OE should be connected to GND through a ...
The HD74LV2GT14A has triple inverters with Schmitt-trigger inputs in an 8 pin package. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logiclevel translator from 3.0 V CMOS Logic ...
The HD74LV2GT157A has 2channel multiplexer in 8 pin package. The input protection circuitry on thi
device allows over voltage tolerance on the input, allowing the device to be used as a logiclevel translato
from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from ...
PI4ULS3V08M, is a 8-bit (octal) non-inverting bus
transceiver with two separate supply rails: A port (VCCA)
and B port (VCCB) are set to operate at 1.2V to 3.6V. This
arrangement permits universal bidirectional translation of
differential signal ...
Pericom Semiconductors PI4ULS3V16 is a 16-bit (dual-octal)
non-inverting bus transceiver with two separate supply rails.
A port (VCCA) and B port (VCCB) are set to operate at 1.2V to
3.6V. This arrangement permits universal bidirectional translation
of ...
CD40109BMS contains four low-to-high voltage level shifting
circuits. Each circuit will shift a low voltage digital logic input
signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS
to a higher voltage output signal (E, F, G, H) with logical
1 = VDD ...
The 74HC4049 is a high-speed Si-gate CMOS device and
is pin compatible with the 4049 of the 4000B series. It
is specified in compliance with JEDEC standard no. 7A.
The 74HC4049 provides six inverting buffers with a
modified input protection structure, ...
The 74HC4050 is a high-speed Si-gate CMOS device and
is pin compatible with the 4050 of the 4000B series. It
is specified in compliance with JEDEC standard no. 7A.
The 74HC4050 provides six non-inverting buffers with a
modified input protection structure, ...
