128m Double Data Rate Synchronous Dram Electric Semiconductor

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM with SSTL_2 Interface All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems. By Mitsumi Electronics, Corp.
M2S28D20ATP 's PackagesM2S28D20ATP 's pdf datasheet

M2S28D20ATP Pinout, Pinouts
M2S28D20ATP pinout,Pin out
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