512 Mbit (4 Banks X 8M X 16) , 133 MHz Clock Rate, Bare Die, 1.8V Supply, Low Power SDRAMThe M65KA512AB is a 512 Mbit Low Power Synchronous DRAM (SDRAM). The memory
array is organized as 4 Banks of 8,388,608 words of 16 bits each.
The LPSDRAM achieves low power consumption and high-speed data transfer using the
pipeline architecture. By STMicroelectronics
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| M65KA512AB Pb-Free | M65KA512AB Cross Reference | M65KA512AB Schematic | M65KA512AB Distributor |
| M65KA512AB Application Notes | M65KA512AB RoHS | M65KA512AB Circuits | M65KA512AB footprint |
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