512Mbit (4 Banks X 4M X 32) , 133MHz Clock Rate,1.8 V Supply, Low Power SDRAM

The M65KC512AB is a 512Mbit Low Power Synchronous DRAM (SDRAM). The memory array is organized as 4 Banks of 4,194,304 Words of 32 bits each. The LPSDRAM achieves low power consumption and high-speed data transfer using the pipeline architecture. It is well suited for handheld battery powered applications like PDAs, 2.5 and 3G mobile phones and handheld computers. By STMicroelectronics
M65KC512AB 's PackagesM65KC512AB 's pdf datasheet
M65KC512AB8W8




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M65KC512AB circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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