1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAM

The M68AF127B is a 1Mbit (1,048,576 bit) CMOS SRAM organized as 131,072 words by 8 bits. The device features fully static operation requiring no external Clocks or Timing strobes, with equal ad- dress access and cycle times. It requires a single 4.5 to 5.5V supply. By STMicroelectronics
M68AF127B 's PackagesM68AF127B 's pdf datasheet
M68AF127BM70B6U
M68AF127BM70MC6T
M68AF127BM70N6
M68AF127BM70N6T

M68AF127B pdf datasheet download


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