MAX3874 2.488Gbps/2.667Gbps Clock And Data Recovery With Limiting Amplifier

The MAX3874 is a compact, dual-rate Clock and data recovery with Limiting Amplifier for OC-48 and OC-48 with FEC SONET SDH applications. Without using an external reference Clock the fully integrated phaselocked loop (PLL) recovers a synchronous Clock signal from the serial NRZ data input. The input data is then retimed by this recovered Clock providing a clean data output. An additional serial input (SLBI) is available for system-loopback diagnostic testing. Alternatively, this input CAN be connected to a reference Clock to maintain a valid Clock output in the absence of data transitions. The device also includes a loss-of-lock (LOL-bar) output.
The MAX3874 contains a vertical threshold control to compensate for optical noise due to EDFAs in DWDM transmission systems. The recovered data and Clock outputs are CML with on-chip 50 back termination on each line. Its jitter performance exceeds all SONET SDH specifications. The MAX3874A is the MAX3874 with a Voltage-Controlled Oscillator (VCO) centered at 2.0212GHz.
The MAX3874 operates from a single +3.3V supply and typically consumes 580mW. It is available in a 5mm x 5mm 32-pin QFN with exposed pad package and operates over the -40C to +85C temperature range.
By Maxim Integrated Products
MAX3874 's PackagesMAX3874 's pdf datasheet

MAX3874 Pinout, Pinouts
MAX3874 pinout,Pin out
This is one package pinout of MAX3874,If you need more pinouts please download MAX3874's pdf datasheet.

MAX3874 Application circuits
MAX3874 circuits
This is one application circuit of MAX3874,If you need more circuits,please download MAX3874's pdf datasheet.

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