MAX5865 Ultra-Low-Power, High-Dynamic-Performance, 40Msps Analog Front End

The MAX5865 ultra-low-power, highly integrated Analog front end is ideal for portable Communication equipment such as handsets, PDAs, WLAN, and 3G Wireless terminals. The MAX5865 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' Analog I-Q input Amplifiers are fully differential and accept 1VP-P full-scale signals. Typical I-Q channel phase matching is 0.2 and amplitude matching is 0.05dB. The ADCs feature 48.4dB SINAD and 70dBc spurious-free dynamic range (SFDR) at fIN = 5.5MHz and fCLK = 40MHz. The DACs' Analog I-Q outputs are fully differential with 400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase matching is 0.15 and gain matching is 0.05dB. The DACs also feature dual 10-bit resolution with 72dBc SFDR, and 57dB SNR at fOUT = 2.2MHz and fCLK = 40MHz.
The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial Interface controls power-down and transceiver modes of operation. The typical operating power is 75.6mW at fCLK = 40Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5865 features an internal 1.024V Voltage Reference that is stable over the entire operating power-supply range and temperature range. The MAX5865 operates on a +2.7V to +3.3V Analog power supply and a +1.8V to +3.3V digital I/O power supply for Logic compatibility. The quiescent current is 8.5mA in idle mode and 1A in shutdown mode. The MAX5865 is specified for the extended (-40C to +85C) temperature range and is available in a 48-pin thin QFN package. See a parametric table of the complete family of pin-compatible AFEs.
By Maxim Integrated Products
MAX5865 's PackagesMAX5865 's pdf datasheet

MAX5865 Pinout, Pinouts
MAX5865 pinout,Pin out
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