Dual 9-bit D-type Flip-flop With Reset And Enable 3-state

The MB2823 dual bus Interface Register is designed to eliminate the extra packages required to Buffer existing Registers and provide extra data width for wider data/address paths of buses carrying parity. The MB2823 has two 9-bit wide buffered Registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. By NXP Semiconductors
MB2823 's PackagesMB2823 's pdf datasheet

MB2823 Pinout, Pinouts
MB2823 pinout,Pin out
This is one package pinout of MB2823,If you need more pinouts please download MB2823's pdf datasheet.

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MB2823 Application Notes MB2823 RoHS MB2823 Circuits MB2823 footprint
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